US Patent Issued to Intel on June 10 for "Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy" (Oregon Inventors)

ALEXANDRIA, Va., June 18 -- United States Patent no. 12,328,920, issued on June 10, was assigned to Intel Corp. (Santa Clara, Calif.).

"Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy" was invented by William Hsu (Portland, Ore.), Biswajeet Guha (Hillsboro, Ore.), Chung-Hsun Lin (Portland, Ore.), Anand S. Murthy (Portland, Ore.) and Tahir Ghani (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Gate-all-around integrated circuit structures having nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy, are described. For example, an integrated circuit structure includes a plurality of horizon...