US Patent Issued to Intel on July 22 for "Simultaneous filling of variable aspect ratio single damascene contact to gate and trench vias with low resistance barrierless selective metallization" (Oregon Inventors)

ALEXANDRIA, Va., July 23 -- United States Patent no. 12,368,095, issued on July 22, was assigned to Intel Corp. (Santa Clara, Calif.).

"Simultaneous filling of variable aspect ratio single damascene contact to gate and trench vias with low resistance barrierless selective metallization" was invented by AKM Shaestagir Chowdhury (Portland, Ore.), Debashish Basu (Beaverton, Ore.), Githin F. Alapatt (Portland, Ore.), Justin E. Mueller (Portland, Ore.) and James Y. Jeong (Beaverton, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An integrated circuit structure comprises a first metal layer having first conductive features. A second metal layer has second conductive features. A via layer is in an insulating l...