US Patent Issued to Intel on July 22 for "Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure" (Oregon Inventors)

ALEXANDRIA, Va., July 23 -- United States Patent no. 12,369,399, issued on July 22, was assigned to Intel Corp. (Santa Clara, Calif.).

"Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure" was invented by Willy Rachmady (Beaverton, Ore.), Sudipto Naskar (Portland, Ore.), Cheng-Ying Huang (Hillsboro, Ore.), Gilbert Dewey (Beaverton, Ore.), Marko Radosavljevic (Portland, Ore.), Nicole K. Thomas (Portland, Ore.), Patrick Morrow (Portland, Ore.) and Urusa Alaan (Hillsboro, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An integrated circuit structure having a stacked transistor architecture includes a first semiconductor body (e.g., set of one or more nan...