ALEXANDRIA, Va., July 16 -- United States Patent no. 12,362,306, issued on July 15, was assigned to Intel Corp. (Santa Clara, Calif.).
"Clock-gating in die-to-die (D2D) interconnects" was invented by Narasimha Lanka (Dublin, Calif.), Debendra Das Sharma (Saratoga, Calif.), Lakshmipriya Seshan (Sunnyvale, Calif.), Gerald Pasdast (San Jose, Calif.), Zuoguo Wu (San Jose, Calif.) and Swadesh Choudhary (Mountain View, Calif.).
According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may...