US Patent Issued to Intel on Feb. 3 for "Lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors" (Oregon Inventors)

ALEXANDRIA, Va., Feb. 3 -- United States Patent no. 12,541,416, issued on Feb. 3, was assigned to Intel Corp. (Santa Clara, Calif.).

"Lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors" was invented by Gaurav Porwal (Portland, Ore.), Theodros Yigzaw (Sherwood, Ore.), Subhankar Panda (Portland, Ore.) and John Holm (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Methods and apparatus relating to lane based normalized historical error counter view for faulty lane isolation and disambiguation of transient versus persistent errors are described. In an embodiment, a plurality of storage entries store error informatio...