US Patent Issued to Intel on Dec. 16 for "Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition" (Oregon Inventors)

ALEXANDRIA, Va., Dec. 16 -- United States Patent no. 12,500,162, issued on Dec. 16, was assigned to Intel Corp. (Santa Clara, Calif.).

"Staggered vertically spaced integrated circuit line metallization with differential vias and metal-selective deposition" was invented by Elijah Karpov (Portland, Ore.), Miriam Reshotko (Portland, Ore.), Scott B. Clendenning (Portland, Ore.), Jiun-Ruey Chen (Hillsboro, Ore.) and Matthew Metz (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Adjacent interconnect lines are in staggered, vertically spaced positions, which accordingly reduces their capacitive coupling within one level of interconnect metallization. Short and tall interconnect via openings are landed...