US Patent Issued to Intel NDTM US on July 15 for "Read latency reduction for partially-programmed block of non-volatile memory" (California Inventors)

ALEXANDRIA, Va., July 16 -- United States Patent no. 12,362,016, issued on July 15, was assigned to Intel NDTM US LLC (Santa Clara, Calif.).

"Read latency reduction for partially-programmed block of non-volatile memory" was invented by Joseph F. Doller (El Dorado Hills, Calif.), Kristopher H. Gaewsky (El Dorado Hills, Calif.) and Noah Mebane (Sacramento, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent r...