US Patent Issued to Intel Corportation on Nov. 25 for "System, method and apparatus for reducing power consumption of error correction coding using compacted data blocks" (American, Chinese Inventors)

ALEXANDRIA, Va., Nov. 25 -- United States Patent no. 12,481,553, issued on Nov. 25, was assigned to Intel Corportation (Santa Clara, Calif.).

"System, method and apparatus for reducing power consumption of error correction coding using compacted data blocks" was invented by Qiuxu Zhuo (Shanghai), Karthik Ananthanarayanan (Milpitas, Calif.), Hsing-Min Chen (Santa Clara, Calif.), John Holm (Beaverton, Ore.) and Anthony Luck (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "In one embodiment, an apparatus comprises: a first circuit to compact a plurality of data blocks to a compacted data block and to compact a plurality of error correction codes (ECCs) associated with the plurality of data block...