US Patent Issued to Intel Corportaion on Jan. 28 for "Dynamic gate steps for last-level programming to improve write performance" (California Inventors)

ALEXANDRIA, Va., Jan. 29 -- United States Patent no. 12,211,563, issued on Jan. 28, was assigned to Intel Corportaion (Santa Clara, Calif.).

"Dynamic gate steps for last-level programming to improve write performance" was invented by Sagar Upadhyay (Folsom, Calif.), Archana Tankasala (Santa Clara, Calif.), Aliasgar S. Madraswala (Folsom, Calif.) and Shantanu Rajwade (Santa Clara, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a pr...