US Patent Issued to GLOBALFOUNDRIES U.S. on Jan. 20 for "Memory cell array structure having bit line for reducing signal resistance, memory device including the same, and method of forming the same" (New York, California Inventors)

ALEXANDRIA, Va., Jan. 20 -- United States Patent no. 12,532,482, issued on Jan. 20, was assigned to GLOBALFOUNDRIES U.S. Inc. (Malta, N.Y.).

"Memory cell array structure having bit line for reducing signal resistance, memory device including the same, and method of forming the same" was invented by Sandeep Puri (Ballston Lake, N.Y.), Venkatesh Periyapatna Gopinath (Fremont, Calif.) and Bipul C. Paul (Mechanicville, N.Y.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A memory cell array structure includes a memory cell including a memory element and a transistor having a source terminal coupled to a second electrode of the memory element, a bit line coupled to a drain terminal of the transistor and including ...