US Patent Issued to Cadence Design Systems on Nov. 18 for "System and method for comparing circuit design constraint sets" (American, Indian Inventors)

ALEXANDRIA, Va., Nov. 18 -- United States Patent no. 12,475,286, issued on Nov. 18, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"System and method for comparing circuit design constraint sets" was invented by Jeannette Newman Sutherland (Cedar Park, Texas), Amit Dhuria (Fremont, Calif.), Arvind Nembili Veeravalli (Bangalore, India), Sarath Jayalath Kirihennedige (Fair Oaks, Calif.) and Saulius Kersulis (Pleasanton, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments included herein are directed towards a method for comparing constraint sets. The embodiments may include determining, using at least one processor, at least one arrival propagation time corresponding to at least ...