US Patent Issued to Cadence Design Systems on Nov. 18 for "Clock-based test-point flop sharing in a circuit design" (Indian, American Inventors)

ALEXANDRIA, Va., Nov. 18 -- United States Patent no. 12,475,288, issued on Nov. 18, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Clock-based test-point flop sharing in a circuit design" was invented by Brian Foutz (Charlottesville, Va.), Vivek Chickermane (Slaterville Springs, N.Y.), Bharath Nandakumar (New Delhi), Sameer Chakravarthy Chillarige (Bengaluru, India), Krishna Chakravadhanula (Vestal, N.Y.), Prateek Kumar Rai (Uttar Pradesh, India) and Sarthak Singhal (Noida-Uttar Pradesh, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "A system includes a memory that stores instructions and receives a circuit netlist, and includes a processing unit that accesses the memory and executes ...