US Patent Issued to Cadence Design Systems on June 24 for "Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis" (Texas Inventors)

ALEXANDRIA, Va., June 25 -- United States Patent no. 12,339,701, issued on June 24, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis" was invented by Yi-Xiao Ding (Austin, Texas), Sheng-En David Lin (Austin, Texas), Natarajan Viswanathan (Austin, Texas) and Charles Jay Alpert (Cedar Park, Texas).

According to the abstract* released by the U.S. Patent & Trademark Office: "Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, wherein the clock signal layout comprises a clock source electrically coupled to a plurality of c...