US Patent Issued to Cadence Design Systems on Feb. 3 for "Clock gating" (Indian Inventors)

ALEXANDRIA, Va., Feb. 3 -- United States Patent no. 12,541,223, issued on Feb. 3, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Clock gating" was invented by Kandregula Uma Suri Appa Rao (Munagapaka, India) and Udatha Sambasiva Rao (Andhra Pradesh, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "During a low power mode, a fast clock may not be provided to serial/parallel conversion circuitry. An asynchronous gating signal that controls the gating of the fast clock may be synchronized to a slow clock and the fast clock. The frequency of the fast clock may be an integer multiple of the slow clock, such that gating the fast clock based on the fast-slow clock synchronized gating signal re...