US Patent Issued to Cadence Design Systems on Aug. 19 for "Power consumption estimation of memory under test" (American, Indian Inventors)

ALEXANDRIA, Va., Aug. 20 -- United States Patent no. 12,393,246, issued on Aug. 19, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Power consumption estimation of memory under test" was invented by Puneet Arora (Austin, Texas), Mohit Madaan (Gurugram, India), Norman Card (Vestal, N.Y.) and Carl Wisnesky II (Apalachin, N.Y.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Various embodiments provide for estimating power consumption by one or more memory components of a circuit design during memory testing, which can be used as part of an electronic design automation (EDA) software."

The patent was filed on Jan. 5, 2024, under Application No. 18/405,820.

*For further information, including im...