US Patent Issued to Bayes Electronics Technology on Dec. 9 for "System and method for identifying design faults or semiconductor modeling errors by analyzing failed transient simulation of an integrated circuit" (Chinese Inventor)

ALEXANDRIA, Va., Dec. 9 -- United States Patent no. 12,493,072, issued on Dec. 9, was assigned to Bayes Electronics Technology Co. Ltd (Shaoxing, China).

"System and method for identifying design faults or semiconductor modeling errors by analyzing failed transient simulation of an integrated circuit" was invented by Gang Peter Fang (Zhejiang, China).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method for detecting non-convergence error in a transient circuit simulation wherein a circuit netlist and control statements associated with a circuit for the transient circuit simulation are received. A transient circuit simulation is performed responsive to a time point. Whether a non-convergence error has occur...