ALEXANDRIA, Va., June 18 -- United States Patent no. 12,328,872, issued on June 10, was assigned to Applied Materials Inc. (Santa Clara, Calif.).
"Liner for V-NAND word line stack" was invented by Jacqueline S. Wrench (San Jose, Calif.), Yixiong Yang (Fremont, Calif.), Yong Wu (Sunnyvale, Calif.), Wei V. Tang (Santa Clara, Calif.), Srinivas Gandikota (Santa Clara, Calif.), Yongjing Lin (San Jose, Calif.), Karla M Bernal Ramos (San Jose, Calif.) and Shih Chung Chen (Cupertino, Calif.).
According to the abstract* released by the U.S. Patent & Trademark Office: "Methods of forming memory structures are discussed. Specifically, methods of forming 3D NAND devices are discussed. Some embodiments form memory structures with a metal nitride barri...