US Patent Issued to Altera on April 8 for "Dynamically scalable timing and power models for programmable logic devices" (American, Canadian, Indian Inventors)

ALEXANDRIA, Va., April 9 -- United States Patent no. 12,273,107, issued on April 8, was assigned to Altera Corp. (San Jose, Calif.).

"Dynamically scalable timing and power models for programmable logic devices" was invented by Atul Maheshwari (Portland, Ore.), Mahesh Iyer (Fremont, Calif.), Mahesh K. Kumashikar (Bangalore, India), Ian Kuon (Toronto), Yuet Li (Fremont, Calif.), Ankireddy Nalamalpu (Portland, Ore.) and Dheeraj Subbareddy (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments of the present disclosure are related to dynamically adjusting a timing and/or power model for a programmable logic device. In particular, the present disclosure is directed to adjusting a timing and/or...