US Patent Issued to Advanced Micro Devices on May 20 for "Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches" (Texas, Colorado, Massachusetts Inventors)

ALEXANDRIA, Va., June 16 -- United States Patent no. 12,306,754, issued on May 20, was assigned to Advanced Micro Devices Inc (Santa Clara, Calif.).

"Method and apparatus for increasing memory level parallelism by reducing miss status holding register allocation in caches" was invented by Jagadish B. Kotra (Austin, Texas), John Kalamatianos (Arlington, Mass.), Paul James Moyer (Fort Collins, Colo.), Nicholas Dean Lance (Windsor, Colo.), Sriram Srinivasan (Cedar Park, Texas), Patrick James Shyvers (Fort Collins, Colo.) and William Louie Walker (Fort Collins, Colo.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An entry of a last level cache shadow tag array to track pending last level cache misses to private ...