ALEXANDRIA, Va., Nov. 18 -- United States Patent no. 12,476,212, issued on Nov. 18, was assigned to Adeia Semiconductor Technologies LLC (San Jose, Calif.).
"3D-interconnect" was invented by Chok J. Chia (Cupertino, Calif.), Qwai H. Low (Cupertino, Calif.) and Patrick Variot (Los Gatos, Calif.).
According to the abstract* released by the U.S. Patent & Trademark Office: "A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuou...