US Patent Issued to Adeia Semiconductor Technologies on March 18 for "Scalable architecture for reduced cycles across SOC" (Colorado, California Inventors)

ALEXANDRIA, Va., March 19 -- United States Patent no. 12,255,176, issued on March 18, was assigned to Adeia Semiconductor Technologies LLC (San Jose, Calif.).

"Scalable architecture for reduced cycles across SOC" was invented by Javier A. DeLaCruz (San Jose, Calif.) and Richard E. Perego (Thornton, Colo.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A microelectronic assembly may include a semiconductor wafer having first and second surfaces extending in first and second directions, the semiconductor wafer having network nodes connected to one another via local adjacent connections each extending in only one of the first and second directions, and an interconnection structure comprising a low-loss dielectri...