US Patent Issued to Adeia Semiconductor on Aug. 26 for "3D processor having stacked integrated circuit die" (California Inventors)

ALEXANDRIA, Va., Aug. 26 -- United States Patent no. 12,401,010, issued on Aug. 26, was assigned to Adeia Semiconductor Inc. (San Jose, Calif.).

"3D processor having stacked integrated circuit die" was invented by Steven L. Teig (Menlo Park, Calif.), Ilyas Mohammed (Santa Clara, Calif.), Kenneth Duong (San Jose, Calif.) and Javier DeLaCruz (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more ...