ALEXANDRIA, Va., Sept. 30 -- United States Patent no. 12,431,899, issued on Sept. 30.
"Self-gating flops for dynamic power reduction" was invented by Mahesh K. Kumashikar (Bangalore, India), Md Altaf Hossain (Portland, Ore.), Yuet Li (Fremont, Calif.), Atul Maheshwari (Portland, Ore.) and Ankireddy Nalamalpu (Portland, Ore.).
According to the abstract* released by the U.S. Patent & Trademark Office: "Systems or methods described herein may relate to latch-independent clock gating techniques to enable or disable an internal clock of an integrated circuit device. A programmable logic device includes a clock gating circuit that receives a clock signal and is latch independent. The clock gating circuit includes gating signal circuitry that ge...