US Patent Issued on Sept. 23 for "Memory devices with multiple sets of latencies and methods for operating the same" (Japanese, American Inventors)

ALEXANDRIA, Va., Sept. 23 -- United States Patent no. 12,423,010, issued on Sept. 23.

"Memory devices with multiple sets of latencies and methods for operating the same" was invented by Dean D. Gans (Nampa, Idaho), Yoshiro Riho (Tokyo), Shunichi Saito (Kanagawa, Japan) and Osamu Nagashima (Tokyo).

According to the abstract* released by the U.S. Patent & Trademark Office: "Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory d...