US Patent Issued on Nov. 4 for "Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same" (Idaho, Texas, California, Arizona Inventors)

ALEXANDRIA, Va., Nov. 6 -- United States Patent no. 12,463,044, issued on Nov. 4.

"Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same" was invented by Baosuo Zhou (Boise, Idaho), Mirzafer K. Abatchev (Fremont, Calif.), Ardavan Niroomand (Boise, Idaho), Paul A. Morgan (Kuna, Idaho), Shuang Meng (Austin, Texas), Joseph Neil Greeley (Boise, Idaho) and Brian J. Coppa (Tempe, Ariz.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrifi...