INTERNATIONAL PATENT: THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A. FILES APPLICATION FOR "THREAD TILING FOR MEMORY LATENCY REDUCTION"

GENEVA, June 10 -- THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A. (Patras Science Park26504 Rion Achaias) filed a patent application (PCT/GR2023/000063) for "THREAD TILING FOR MEMORY LATENCY REDUCTION" on Nov 27, 2023. With publication no. WO/2025/114731, the details related to the patent application was published on Jun 05, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): BARTSOKAS, Anastasios (c/o Think Silicon Research and Technology Single Member S.A.Patras Science Park26504 Rion Achaias), GEORGAKAKIS, Dimitris (c/o Think Silicon Research and Technology Single Member S.A.Patras ...