INTERNATIONAL PATENT: POWERLATTICE TECHNOLOGIES INC. FILES APPLICATION FOR "POWER MANAGEMENT TECHNIQUES USING LOCATION-MAPPED CHIPLET CONFIGURATION"

GENEVA, June 25 -- POWERLATTICE TECHNOLOGIES INC. (2005 Se 192nd Ave. Suite 200Camas, WA 98607) filed a patent application (PCT/US2024/060227) for "POWER MANAGEMENT TECHNIQUES USING LOCATION-MAPPED CHIPLET CONFIGURATION" on Dec 13, 2024. With publication no. WO/2025/129134, the details related to the patent application was published on Jun 19, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): ZOU, Peng (2005 SE 192nd Ave. Suite 200Camas, WA 98607), REN, Gang (2005 SE 192nd Ave. Suite 200Camas, WA 98607), DERMAL, Sujith (2005 SE 192nd Ave. Suite 200Camas, WA 98607)

Abstract: This application...