GENEVA, April 21 -- NEO SEMICONDUCTOR, INC. (1871 The Alameda, Suite 250San Jose, California 95126) filed a patent application (PCT/US2024/051152) for "3D MEMORY CELLS AND ARRAY ARCHITECTURES AND PROCESSES" on Oct 11, 2024. With publication no. WO/2025/081125, the details related to the patent application was published on Apr 17, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): HSU, Fu-Chang (1228 Cordelia Ave.San Jose, California 95129), HUANG, Richard J. (3901 Borgo CommonFREMONT, California 94538)

Abstract: Various 3D memory cells, array architectures, and processes are disclosed. In an...