INTERNATIONAL PATENT: MURATA MANUFACTURING CO., LTD. FILES APPLICATION FOR "REDUCTION OF EDGE TRANSISTOR LEAKAGE OF N-TYPE EDMOS AND LDMOS DEVICES"

GENEVA, March 25 -- MURATA MANUFACTURING CO., LTD. (10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto6178555) filed a patent application (PCT/JP2024/031783) for "REDUCTION OF EDGE TRANSISTOR LEAKAGE OF N-TYPE EDMOS AND LDMOS DEVICES" on Sep 04, 2024. With publication no. WO/2025/057843, the details related to the patent application was published on Mar 20, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): SINGH, Jagar (c/o pSemi Corporation, 9369 Carroll Park Drive, San Diego, California92121), SAJI, Mari (c/o pSemi Corporation, 9369 Carroll Park Drive, San Diego, California92121), FUJIHARA, ...