INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "WEAR LEVELING IN A ZONED NAMESPACE MEMORY SUB-SYSTEM"

GENEVA, Nov. 18 -- MICRON TECHNOLOGY, INC. (8000 So. Federal WayBoise, Idaho 83716-9632) filed a patent application (PCT/US2025/027730) for "WEAR LEVELING IN A ZONED NAMESPACE MEMORY SUB-SYSTEM" on May 05, 2025. With publication no. WO/2025/235369, the details related to the patent application was published on Nov 13, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): LI, Juane (639 Mercado CourtMilpitas, 95035), ZHU, Fangfang (801 S Winchester BlvdApt 4206San Jose, California 95128)

Abstract: A memory device comprises multiple quad-level cell (QLC) block sets and multiple single-level cell (S...