INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES"

GENEVA, April 16 -- MICRON TECHNOLOGY, INC. (8000 S. Federal WayBoise, Idaho 83716-9632) filed a patent application (PCT/US2024/049476) for "TECHNIQUES FOR SEMICONDUCTOR DIE COUPLING IN STACKED MEMORY ARCHITECTURES" on Oct 01, 2024. With publication no. WO/2025/075998, the details related to the patent application was published on Apr 10, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): BHUSHAN, Bharat (8000 S. Federal WayBoise, Idaho 83716-9632), PAREKH, Kunal, R. (8000 S. Federal WayBoise, Idaho 83716-9632), SINGH, Akshay, N. (8000 S. Federal WayBoise, Idaho 83716-9632)

Abstract: Methods...