INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "STACKED SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR DIES OF VARIABLE SIZE"

GENEVA, May 14 -- MICRON TECHNOLOGY, INC. (8000 S. Federal Way, P.O. Box 6Boise, ID 83707-0006) filed a patent application (PCT/US2024/051739) for "STACKED SEMICONDUCTOR DEVICE WITH SEMICONDUCTOR DIES OF VARIABLE SIZE" on Oct 17, 2024. With publication no. WO/2025/096213, the details related to the patent application was published on May 08, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): BHUSHAN, Bharat (C/o Micron Technology, Inc.8000 S. Federal Way, P.O. Box 6Boise, ID 83707-0006), SINGH, Akshay, N. (C/o Micron Technology, Inc.8000 S. Federal Way, P.O. Box 6Boise, ID 83707-0006), PAREKH, ...