INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "STACKED DIE SUBSTRATE-LESS SEMICONDUCTOR PACKAGE"

GENEVA, Feb. 4 -- MICRON TECHNOLOGY, INC. (8000 South Federal Way, Post Office Box 6Boise, Idaho 83707-0006) filed a patent application (PCT/US2025/037387) for "STACKED DIE SUBSTRATE-LESS SEMICONDUCTOR PACKAGE" on Jul 11, 2025. With publication no. WO/2026/024486, the details related to the patent application was published on Jan 29, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): KUMAR, Gokul (4425 Cherico LaneDublin, California 94568), TAKIAR, Hem P. (1544 Blackfoot DriveFremont, California 94539)

Abstract: Implementations described herein relate to various semiconductor device assemblies...