GENEVA, Oct. 20 -- MICRON TECHNOLOGY, INC. (Mail Stop 5078000 South Federal WayP.O. Box 6Boise, Idaho 83707-0006) filed a patent application (PCT/US2025/024043) for "PROCESSING A MEMORY ARRAY WITH REDUCED DRIFT" on Apr 10, 2025. With publication no. WO/2025/217388, the details related to the patent application was published on Oct 16, 2025.
Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).
Inventor(s): PIROVANO, Agostino (Via Pompeo Marchesi, 5720153 Milano), TORTORELLI, Innocenzo (Via Verdi 2A20063 Cernusco sul Naviglio), VORA, Nirav (5967 W Daphne Dr.Meridian, Idaho 83646)
Abstract: Processing a memory array ...