GENEVA, July 3 -- MICRON TECHNOLOGY, INC. (8000 So. Federal WayBoise, Idaho 83716-9632) filed a patent application (PCT/US2024/060208) for "MEMORY ARCHITECTURE FOR BLOCK MIGRATION IN ZNS" on Dec 13, 2024. With publication no. WO/2025/136833, the details related to the patent application was published on Jun 26, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): STONELAKE, Paul (186 Kawailani Cir.Kihei, Hawaii 96753)

Abstract: The disclosure configures a memory sub-system controller to efficiently perform block migration (e.g., from SLC cache to QLC blocks) in a Zone Namespace (ZNS) device. T...