INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "LOGIC-UPPERMOST SEMICONDUCTOR DEVICE ASSEMBLIES WITH RECONSTITUTED WAFERS AND MULTI-RETICLE DIES COUPLED BY RETICLE-BRIDGING CONDUCTORS"

GENEVA, Feb. 11 -- MICRON TECHNOLOGY, INC. (8000 S. Federal Way, P.O. Box 6Boise, ID 83707-0006) filed a patent application (PCT/US2025/039545) for "LOGIC-UPPERMOST SEMICONDUCTOR DEVICE ASSEMBLIES WITH RECONSTITUTED WAFERS AND MULTI-RETICLE DIES COUPLED BY RETICLE-BRIDGING CONDUCTORS" on Jul 28, 2025. With publication no. WO/2026/030256, the details related to the patent application was published on Feb 05, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): BHUSHAN, Bharat (c/o Micron Technology, Inc.8000 S. Federal Way, P.O. Box 6Boise, ID 83707-0006), PAREKH, Kunal R. (c/o Micron Technology, ...