INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "DIE-LEVEL BLOCK FAMILY ERROR AVOIDANCE"

GENEVA, June 25 -- MICRON TECHNOLOGY, INC. (8000 South Federal WayBoise, Idaho 83716) filed a patent application (PCT/US2024/060222) for "DIE-LEVEL BLOCK FAMILY ERROR AVOIDANCE" on Dec 13, 2024. With publication no. WO/2025/129129, the details related to the patent application was published on Jun 19, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): LANG, Murong (1381 Bing DriveSan Jose, California 95129), XU, Zhongguang (1950 Galileo LaneSan Jose, California 95133), CHANG, Li-Te (4120 Barrymore DriveSan Jose, California 95117)

Abstract: A sacrificial block in a die of a plurality of dies ...