INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES"

GENEVA, May 14 -- MICRON TECHNOLOGY, INC. (8000 S. Federal WayBoise, Idaho 83716-9632) filed a patent application (PCT/US2024/039164) for "DATA ROUTING FOR ERROR CORRECTION IN STACKED MEMORY ARCHITECTURES" on Jul 23, 2024. With publication no. WO/2025/096030, the details related to the patent application was published on May 08, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): GUNASEKARAN, Shivasankar (8000 S. Federal WayBoise, Idaho 83716-9632), MYLAVARAPU, Sai Krishna (8000 S. Federal WayBoise, Idaho 83716-9632)

Abstract: Methods, systems, and devices for data routing for error correctio...