INTERNATIONAL PATENT: MICRON TECHNOLOGY, INC. FILES APPLICATION FOR "CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES"

GENEVA, April 1 -- MICRON TECHNOLOGY, INC. (Mail Stop 5078000 South Federal WayP.O. Box 6Boise, Idaho 83707-0006) filed a patent application (PCT/US2024/039294) for "CAPACITANCE BALANCING IN SEMICONDUCTOR DEVICES" on Jul 24, 2024. With publication no. WO/2025/064050, the details related to the patent application was published on Mar 27, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): CARMAN, Eric (8000 S. Federal WayBoise, Idaho 83716), MORZANO, Christopher (8000 S. Federal WayBoise, Idaho 83716)

Abstract: Systems, methods, and apparatus are provided for capacitance balancing in semicondu...