INTERNATIONAL PATENT: MICROCHIP TECHNOLOGY INCORPORATED FILES APPLICATION FOR "PLANAR JFET WITH BURIED GATE"

GENEVA, Feb. 24 -- MICROCHIP TECHNOLOGY INCORPORATED (2355 W. Chandler Blvd.Chandler, Arizona 85224) filed a patent application (PCT/US2025/026682) for "PLANAR JFET WITH BURIED GATE" on Apr 28, 2025. With publication no. WO/2026/039078, the details related to the patent application was published on Feb 19, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): PANDEY, Shesh Mani (5265 S Red Rock StreetGilbert, Arizona 85298), ODEKIRK, Bruce (1985 SW Warwick Ave.Portland, Oregon 97225)

Abstract: A field-effect transistor with a buried gate, and a method of making the same. A volume of semiconductor...