INTERNATIONAL PATENT: CISCO TECHNOLOGY, INC. FILES APPLICATION FOR "LOW LATENCY, LOW LOSS, SCALABLE THROUGHPUT QUEUING AND MARKING"

GENEVA, May 28 -- CISCO TECHNOLOGY, INC. (170 West Tasman DriveSan Jose, California 95134-1706) filed a patent application (PCT/US2024/055961) for "LOW LATENCY, LOW LOSS, SCALABLE THROUGHPUT QUEUING AND MARKING" on Nov 14, 2024. With publication no. WO/2025/106699, the details related to the patent application was published on May 22, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): HART, Brian D. (899 Lois AvenueSunnyvale, California 94087), GUPTA, Binita (16208 Lone WaySan Diego, California 92127), HENRY, Jerome (124 Forest Ridge LanePittsboro, North Carolina 27312), SMITH, Malcolm M. (4601...