GENEVA, May 28 -- CISCO TECHNOLOGY, INC. (170 West Tasman DriveSan Jose, California 95134-1706) filed a patent application (PCT/US2024/055951) for "LOW LATENCY, LOW LOSS, SCALABLE THROUGHPUT LATENCY IMPROVEMENT" on Nov 14, 2024. With publication no. WO/2025/106692, the details related to the patent application was published on May 22, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): ZUNIGA, Juan Carlos (955 Rue GohierVille Saint LaurentMontreal, Quebec H4L 3J4), BARTON, Robert E. (6291 Dunsmuir CrescentRichmond, British Columbia V7C 5R6), HENRY, Jerome (124 Forest Ridge LanePittsboro, North C...