INTERNATIONAL PATENT: ASCENIUM, INC. FILES APPLICATION FOR "PARALLEL PROCESSING ARCHITECTURE WITH BLOCK MOVE BACKPRESSURE"

GENEVA, March 10 -- ASCENIUM, INC. (809 Cuesta Drive, Suite BMountain View, CA 94040) filed a patent application (PCT/US2024/044587) for "PARALLEL PROCESSING ARCHITECTURE WITH BLOCK MOVE BACKPRESSURE" on Aug 30, 2024. With publication no. WO/2025/049849, the details related to the patent application was published on Mar 06, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): FOLEY, Peter (13124 Byrd LnLos Altos Hills, CA 94022)

Abstract: Techniques for monitoring block moves in an array of compute elements and applying backpressure are disclosed. An array of compute elements is accessed. The ...