INTERNATIONAL PATENT: ARTERIS, INC. FILES APPLICATION FOR "REINFORCED LEARNING MODEL FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP (NOC)"

GENEVA, Jan. 13 -- ARTERIS, INC. (900 E. Hamilton Avenue, Suite 300Campbell, CA 95008) filed a patent application (PCT/US2025/036168) for "REINFORCED LEARNING MODEL FOR TOPOLOGY GENERATION OF A NETWORK-ON-CHIP (NOC)" on Jul 01, 2025. With publication no. WO/2026/011014, the details related to the patent application was published on Jan 08, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): CHARIF, Amir (Paris), LECERF, Ugo (Paris), CONTE, Donatello (Paris)

Abstract: A computer-implemented method includes loading a simplistic network-on-chip (NoC) topology that is fully routed, and performing r...