INTERNATIONAL PATENT: ARTERIS, INC. FILES APPLICATION FOR "DESIGN TOOL FOR GENERATION OF A NETWORK-ON-CHIP (NOC) INCLUDING INSERTION OF ADAPTERS IN A PATH"

GENEVA, Jan. 13 -- ARTERIS, INC. (900 E. Hamilton Avenue, Suite 300Campbell, CA 95008) filed a patent application (PCT/US2025/035994) for "DESIGN TOOL FOR GENERATION OF A NETWORK-ON-CHIP (NOC) INCLUDING INSERTION OF ADAPTERS IN A PATH" on Jul 01, 2025. With publication no. WO/2026/010895, the details related to the patent application was published on Jan 08, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): KONE, Chaka (Sevres), CHARIF, Amir (Paris)

Abstract: A design tool is disclosed for generation and synthesis of the network, such as a network-on-chip (NoC). The design tool starts with a ...