GENEVA, Jan. 13 -- ARTERIS, INC. (900 E. Hamilton Avenue, Suite 300Campbell, CA 95008) filed a patent application (PCT/US2025/035997) for "DEADLOCK-FREE MODIFICATION TO NETWORK-ON-CHIP TOPOLOGY" on Jul 01, 2025. With publication no. WO/2026/010896, the details related to the patent application was published on Jan 08, 2026.
Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).
Inventor(s): CHARIF, Amir (Paris)
Abstract: Designing a network-on-chip (NoC) includes accessing an existing NoC topology having existing NoC elements, blockages and existing wire connections. The existing NoC elements include network interfa...