INTERNATIONAL PATENT: APPLIED MATERIALS, INC. FILES APPLICATION FOR "BOTTOM-UP DIELECTRIC GAP-FILL FOR DEVICE ISOLATION DURING SOURCE/DRAIN EPITAXY IN CFET"

GENEVA, July 2 -- APPLIED MATERIALS, INC. (3050 Bowers Ave.P.O. Box 58039Santa Clara, California 95054-3299) filed a patent application (PCT/IB2024/062225) for "BOTTOM-UP DIELECTRIC GAP-FILL FOR DEVICE ISOLATION DURING SOURCE/DRAIN EPITAXY IN CFET" on Dec 04, 2024. With publication no. WO/2025/133794, the details related to the patent application was published on Jun 26, 2025.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): COSTRINI, Gregory (c/o Think Silicon Research and Technology Single Member S.A.Patras Science Park26504 Rion Achaias), YEONG, Sai Hooi (c/o Think Silicon Research and Technolog...