MUMBAI, India, Nov. 14 -- Intellectual Property India has published a patent application (202547096998 A) filed by Intel Corporation, Santa Clara, U.S.A., on Oct. 8, for 'sparsity-based reduction of gate switching in deep neural network accelerators.'
Inventor(s) include Langhammer, Martin; Raha, Arnab; and Power, Martin.
The application for the patent was published on Nov. 14, under issue no. 46/2025.
According to the abstract released by the Intellectual Property India: "Gate switching in deep learning operations can be reduced based on sparsity in the input data. A first element of an activation operand and a first element of a weight operand may be stored in input storage units associated with a multiplier in a processing element. Th...