Intellectual Property India Publishes Patent Application for 'Low-Power 4X4 Mesh Network-On-Chip With Power-Gating And Clock-Gating' Filed by Vellore Institute Of Technology

MUMBAI, India, Jan. 2 -- Intellectual Property India has published a patent application (202541122837 A) filed by Vellore Institute Of Technology, Vellore, Tamil Nadu, on Dec. 5, 2025, for 'low-power 4x4 mesh network-on-chip with power-gating and clock-gating.'

Inventor(s) include Dr. Ragunath G; and Mr. Jalagari Pavan Karthik.

The application for the patent was published on Jan. 2, under issue no. 01/2026.

According to the abstract released by the Intellectual Property India: "The present disclosure provides a Network-on-Chip system (500) having a mesh topology with routers arranged in rows and columns. Each router includes a buffer module for storing incoming data packets, an arbitration logic module for determining output ports based ...