Intellectual Property India Publishes Patent Application for 'High Speed Clock Keeper Domino Logic Circuit Design Using Finfet' Filed by Dudekula Usen; Mr. B. Mahendra; and Rajeev Gandhi Memorial College Of Engineering And Technology

MUMBAI, India, July 11 -- Intellectual Property India has published a patent application (202541060637 A) filed by Dudekula Usen; Mr. B. Mahendra; and Rajeev Gandhi Memorial College Of Engineering And Technology, Nandyal, Andhra Pradesh, on June 25, for 'high speed clock keeper domino logic circuit design using finfet.'

Inventor(s) include Mr. B. Mahendra; Dr. A. Sathish; and Dr. Dudekula Usen.

The application for the patent was published on July 11, under issue no. 28/2025.

According to the abstract released by the Intellectual Property India: "The method of deep sub-micron possesses presented numerous obstacles for the production of semiconductor circuits using CMOS technology, mostly pertaining to power use and propagation latency. In...